Window-type BGA semiconductor package is a very common semiconductor package using a substrate with a wire-bonding slot as a chip carrier. Normally, a semiconductor chip is disposed on the top surface of the substrate and a plurality of external terminals such as solder balls are disposed on the bottom surface of the substrate. Moreover, a plurality of bonding wires pass through the wire-bonding slot to electrically connect the chip and the substrate. The substrate has a plurality of bonding fingers disposed on the bottom surface thereof for wire-bonding connection. In order to enhance bondability of the bonding fingers, it is necessary to form a plating layer on bonding fingers. During substrate manufacturing processes, before forming the wire-bonding slot, a plating bus line is disposed on the bottom surface of the substrate and pass through a pre-routing area of the substrate for the wire-bonding slot to electrically connect the bonding fingers of the substrate by a plurality of plating lines. Accordingly, a substrate plating process can be worked in practice for plating Ni/Au or other metal layers on the surfaces of the bonding fingers. After plating, a wire-bonding slot is formed by routing to remove the plating bus line with the most of the plating lines. However, there are still some plating line stubs remained on the substrate connected to the bonding fingers leading to possible electrical short caused by bonding wires.
As shown in FIG. 1, a conventional window-type BGA semiconductor package 100 primarily comprises a substrate 110, a chip 120, a plurality of bonding wires 130, and an encapsulant 140. The substrate 110 has a top surface 111, a bottom surface 112, a wire-bonding slot 113, and at least a peripheral slot 117. The wire-bonding slot 113 is located at the center of the substrate 110 and the peripheral slots 117 at two opposing sides. As shown in FIG. 2, a plurality of bonding fingers 114 and a plurality of plating line stubs 115 are formed on the bottom surface 112 of the substrate 110 where the plating line stubs 115 electrically connect the bonding fingers 114 and extend to the wire-bonding slot 113. The chip 120 has a plurality of bonding pads 122 formed at the center and at the two opposing sides of the active surface of the chip 120. The active surface of the chip 120 is faced toward and attached to the top surface 111 of the substrate 110 with the bonding pads 122 aligned in the wire-bonding slot 113 and in the peripheral slots 117. The bonding wires 130 pass through the wire-bonding slot 113 and through the peripheral slot 117, respectively, to electrically connect the bonding pads 122 of the chip 120 to the bonding fingers 114 of the substrate 110. Encapsulant 140 is formed over the top surface 111 and partially formed on the bottom surface 112 of the substrate 110 to encapsulate the chip 120 and the bonding wires 130. A plurality of external terminals 150 are bonded to the external pads 116 on the bottom surface 112 of the substrate 110. As shown in FIG. 2 again, the wire-bonding slot 113 is a long and narrow through hole and the plating line stubs 115 are perpendicular to longer sides of the wire-bonding slot 113 but are oblique to the bonding wires 130 in a bottom view of the substrate 120. Moreover, some of the bonding wires 130 are too close or even overpassing the adjacent plating line stubs 115 with no relationship of electrical connections. Once the loop height of the bonding wire 130 is too low or the wire sweep of the bonding wire 130 is occurred due to molding, the bonding wires 130 electrically short with the plating line stubs 115, especially the ends of the bonding wires 130 bonded around the wire-bonding slot 113, as shown in FIG. 1 and FIG. 2, leading to electrical failure of the semiconductor package 100.
The surface layout on the substrate 110 before routing the wire-bonding slot 113 is shown in FIG. 3. A plating bus line 10 is disposed on the bottom surface 112 of the substrate 110 and passes through the wire-bonding slot 113 to connect a plurality of plating lines 11 extending from the bonding fingers 114 where the plating lines 11 are formed in parallel and are perpendicularly connected to the plating bus line 10. The substrate 110 has a pre-routing area which is removed by routing to form the wire-bonding slot 113. The portions of the plating lines 11 remained on the substrate 110 become the plating line stubs 115.